Yield Modelling and Defect Tolerance in VLSI

Yield Modelling and Defect Tolerance in VLSI

Hardback (01 Jan 1988)

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Publisher's Synopsis

Papers of the International Workshop on Designing for Yield, Oxford, July 1987. Objectives include discussion of topics in VLSI and designing integrated circuits to yield targets. On yield loss mechanisms and defect tolerance, alternative prospects, catastrophic yield loss models, parametric yield loss, defect-tolerant architectures, yield predicti

Book information

ISBN: 9780852743980
Publisher: Taylor and Francis
Imprint: CRC Press
Pub date:
DEWEY: 621.38173
DEWEY edition: 19
Language: English
Number of pages: 304
Weight: -1g
Height: 230mm