High-Level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip - Computer Architecture and Design Methodologies
1st ed. 2017
Hardback (05 Jul 2017)
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This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.
Book information
ISBN: | 9789811010729 |
Publisher: | Springer Nature Singapore |
Imprint: | Springer |
Pub date: | 05 Jul 2017 |
Edition: | 1st ed. 2017 |
DEWEY: | 621.38150113 |
DEWEY edition: | 23 |
Language: | English |
Number of pages: | 197 |
Weight: | 4557g |
Height: | 235mm |
Width: | 155mm |
Spine width: | 14mm |