Publisher's Synopsis
Gain compression is a reduction in incremental gain caused by nonlinearity of the transfer function of the amplifying device. Gain compression of gain is caused by non-linear characteristics of the device when run at large amplitudes. As the input level is increased beyond the linear range of the amplifier, gain compression may occur depending on the characteristics of the device. This nonlinearity may be caused by heat due to power dissipation or by overdriving the active device beyond its linear region. It is a large-signal phenomenon of circuits. This may also cause harmonic distortion from the device.
To model this non-linear behavior, a VBE multiplier (Q1, etc.) and Zener (D2), (see Figure 3) are used to mimic the non-linear behavior of the device near where ID shows a maximum. To model the quasi-sat behavior from the lightly doped drain variable resistance, a polynomial voltage controlled modeling circuit (E1) is used to mimic this non-linear aspect of the device.
The gain compression and quai-sat behavior of lightly doped drain MOSFETs can be modeled by using the full gain compression circuit shown in Figure 3. This can be very valuable to accurately simulate the current-voltage behavior of lightly doped drains in high voltage/power MOSFETs. Both the gain compression (gm fall-off) and quasi-sat (variable effective drain resistance) behavior can be accurately modeled and simulated by the subcircuit model shown in Figure 3. By proper setting of the various circuit elements and their model parameters very accurate current-voltage behavior of lightly doped drain MOSFETs can be simulated to obtain accurate gate-source and gate-drain capacitances
