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Wafer-Level Testing and Test During Burn-in for Integrated Circuits

Wafer-Level Testing and Test During Burn-in for Integrated Circuits - Artech House Integrated Microsystems Series

Book (28 Feb 2010)

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Publisher's Synopsis

Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions.

Book information

ISBN: 9781596939899
Publisher: Artech House
Imprint: Artech House
Pub date:
DEWEY: 621.38132
DEWEY edition: 22
Number of pages: 198
Weight: 434g
Height: 164mm
Width: 235mm
Spine width: 18mm