Very-Large-Scale Integration Physical Design Engineering Change Order and Timing Design Rule Check

This book presents an innovative approach to rectify Timing-Design Rule Check (TDRC) violations in Very-Large-Scale Integration (VLSI) chip design. Through the utilization of Tool Command Language (TCL) scripting, this automated solution streamlines the Engineering Change Order (ECO) process, offering efficiency, accuracy, and accessibility. By incorporating various strategies such as cell up-sizing, low threshold voltage cell swapping, and buffer insertion, the authors tackle TDRC violations with precision. Their methodology integrates a slope violation percentage-based guide and net length-based buffer insertion strategy, tailored to address specific violations effectively. Moreover, the proactive integration of a Non-Linear Delay Model (NLDM) look-up table ensures robust timing optimization, preventing hold timing violations. This comprehensive guide navigates fundamental placement rules and ECO implementation, featuring a two-step approach named "make shorts into opens" to resolve violations efficiently. Impressively, the automated TDRC Fixer achieves an 87% TDRC violation fix rate with minimal global timing shifts, showcasing the effectiveness of TCL scripting in VLSI physical design workflows. This book is a must-read for professionals, researchers, and students seeking to enhance their understanding of VLSI chip design methodologies and optimize their ECO workflows with pragmatic and accessible solutions.