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Digital Logic Design Using Verilog

Digital Logic Design Using Verilog Coding and RTL Synthesis

1st ed. 2016

Hardback (21 May 2016)

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Publisher's Synopsis

This book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. This book is organized in such a way that that it can describe a number of RTL design scenarios, from simple to complex. The book constructs the logic design story from the fundamentals of logic design to advanced RTL design concepts. Keeping in view the importance of miniaturization today, the book gives practical information on the issues with ASIC RTL design and how to overcome these concerns. It clearly explains how to write an efficient RTL code and how to improve design performance. The book also describes advanced RTL design concepts such as low-power design, multiple clock-domain design, and SOC-based design. The practical orientation of the book makes it ideal for training programs for practicing design engineers and for short-term vocational programs. The contents of the book will also make ita useful read for students and hobbyists. 

Book information

ISBN: 9788132227892
Publisher: Springer India
Imprint: Springer
Pub date:
Edition: 1st ed. 2016
DEWEY: 621.395
DEWEY edition: 23
Language: English
Number of pages: 416
Weight: 8602g
Height: 235mm
Width: 155mm
Spine width: 28mm