Design of Fast,Low Power 16-bit Multiplier using Vedic Mathematics

Design of Fast,Low Power 16-bit Multiplier using Vedic Mathematics

Paperback (07 Jul 2012)

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Publisher's Synopsis

Low power, high speed binary multiplier is an essential component of digital computers. Many architectures of multiplier based on Booth multiplication and array multiplication algorithms have been implemented. The array multiplier using Wallace tree structure is reported to be fastest and requiring minimum hardware. The speed of a binary multiplier is dominantly determined by the speed of adders used in the multiplier. This work describes a new 20-transistor low power high speed hybrid CMOS full adder and a new carry skip adder suitable for use in multipliers. A new modular design method for design of n x n multipliers using Vedic algorithm for multiplication has been proposed. The proposed design method uses more number of gates than array multiplier using Wallace tree but offers the advantages of simple and systematic interconnection scheme and maximum design reuse.

About the Publisher

LAP Lambert Academic Publishing

Since Lambert Academic Publishing's foundation, thousands of top researchers and renowned scientists have embraced its unprecedented approach to free publishing, thereby making it a leader in the book publishing industry today. Research projects, dissertations, diploma theses, master theses and doctoral theses are given unparalleled visibility and global readership. Our catalogue consists of over 40,000 dissertations and theses, which are produced in the form of high-quality paperbacks in the USA, UK and Germany and distributed through an extensive network of major retailers.

Book information

ISBN: 9783659171192
Publisher: KS Omniscriptum Publishing
Imprint: LAP Lambert Academic Publishing
Pub date:
Language: English
Number of pages: 156
Weight: 236g
Height: 229mm
Width: 152mm
Spine width: 9mm